The present invention relates to integrated circuits, and more particularly to substrate isolation in the integrated circuits.
Substrate isolation regions provide isolation between active device areas of a semiconductor substrate. FIGS. 1-4 illustrate a shallow trench isolation process (STI) described in U.S. Pat. No. 5,960,276 issued Sep. 28, 1999 to Liaw et al., incorporated herein by reference. A pad oxide layer 102 and a silicon nitride barrier layer 106 are deposited over substrate 120 (FIG. 1). Trenches 224 (FIG. 2) are etched in substrate 120 to define active areas 230 (i.e. 230.1, 230.2, 230.3). An oxide liner 234.1 is thermally grown on the surface of trenches 224. The liner formation helps passivate the trench sidewalls, as explained in Wolf, “Silicon Processing for the VLSI Era”, volume 3 (“Submicron Transistor”), 1995, page 368.
Then boron is implanted at an energy between about 15 and 45 KeV, a dose between about 3E12 and 5E13 ions/cm2, and an angle α of 15° to 45° to the substrate surface. The boron implant helps mitigate the inverse narrow width effect. This effect is due to a current leakage path along the trench sidewalls. The current leakage is especially noticeable at small channel widths, causing the threshold voltage to decrease as the channel width decreases. The boron implant creates doped regions 242 at the sidewall and bottom surfaces of trenches 224.
FIG. 3 illustrates subsequent processing. Dielectric 234.2 has been formed in trenches 224, and the layers 102, 106 have been removed. Due to the boron diffusion, the doped regions 242 have spread into the active areas 230.
Then a gate line 410 (FIG. 4, top view) is formed to provide the transistor gates. The boron implant (FIG. 2) reduces the current leakage along the channel areas 420.
FIGS. 5-8 illustrate another substrate isolation process, described in K. Shibahara et al., “TRENCH ISOLATION WITH ∇(NABLA)-SHAPED BURIED OXIDE FOR 256-BIT DRAMS”, IEDM 1992, pages 275-278, incorporated herein by reference. This process creates both LOCOS and STI isolation regions in the same substrate. LOCOS is used for wider isolation regions, and STI for narrower regions. LOCOS regions 510 are formed first. Then gate oxide 520, gate polysilicon 410, and cap oxide 530 are formed. Tapered trenches 224 (FIG. 6) are dry-etched with oxide 530 as a mask. Boron is vertically implanted into the trenches for suppression of sidewall inversion. Doped regions 242 are formed as a result. Reference numerals 230.1, 230.2, 230.3 denote the active areas.
The trenches are filled with silicon dioxide 234 (FIG. 7), and the structure is planarized. WSi layer 810 (FIG. 8) is sputtered on the structure. Layers 810, 410 are etched to form polyside gate electrodes.
Alternative substrate isolation techniques are desirable.